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Disambiguation of "Takeda, Koichi"

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An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield.

, , , , , , , , , , , and . IEEE J. Solid State Circuits, 36 (3): 510-515 (2001)

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Genichiro Takeda

Koichi Matsumoto

Michiko Takeda

Kijuro Takeda

Koichi Koshi

 

Other publications of authors with the same name

A 24MB Embedded Flash System Based on 28nm SG-MONOS Featuring 240MHz Read Operations and Robust Over-The-Air Software Update for Automotive., , , , , , , , , and . VLSI Circuits, page 210-. IEEE, (2019)Personalized Web Knowledge Management., and . Web Intelligence, volume 2198 of Lecture Notes in Computer Science, page 200-204. Springer, (2001)Sentence Representations via Gaussian Embedding., , , and . CoRR, (2023)Fully decentralized control of a soft-bodied robot inspired by true slime mold., , , , and . Biol. Cybern., 102 (3): 261-269 (2010)MedTAKMI-CDI: Interactive knowledge discovery for clinical decision intelligence., , , and . IBM Syst. J., 46 (1): 115-134 (2007)A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM., , , , , , , , and . IEEE J. Solid State Circuits, 31 (11): 1610-1617 (1996)A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 35 (11): 1631-1640 (2000)Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes., , , , , and . IEEE J. Solid State Circuits, 41 (4): 805-814 (2006)An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield., , , , , , , , , and 2 other author(s). CICC, page 283-286. IEEE, (2000)Shalt2 - a Symmetric Machine Translation System with Conceptual Transfer., , , and . COLING, page 1034-1038. (1992)