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Efficient Layout Hotspot Detection via Binarized Residual Neural Network Ensemble.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (7): 1476-1488 (2021)

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VLSI layout hotspot detection based on discriminative feature extraction., , , and . APCCAS, page 542-545. IEEE, (2016)Voltage-island driven floorplanning considering level-shifter positions., , , and . ACM Great Lakes Symposium on VLSI, page 51-56. ACM, (2009)GAN-OPC: mask optimization with lithography-guided generative adversarial nets., , , , and . DAC, page 131:1-131:6. ACM, (2018)A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders., , , and . ISLPED, page 1-6. IEEE, (2017)The emotional world of health online communities.. iConference, page 806-807. ACM, (2011)Smart building uncertainty analysis via adaptive Lasso., and . IET Cyper-Phys. Syst.: Theory & Appl., 2 (1): 42-48 (2017)Deep Learning-Driven Simultaneous Layout Decomposition and Mask Optimization., , , , , and . DAC, page 1-6. IEEE, (2020)MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (6): 1237-1250 (2018)Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (5): 726-739 (2015)Adaptive 3D-IC TSV Fault Tolerance Structure Generation., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (5): 949-960 (2019)