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Disambiguation of "Chang, Muya"

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A FeFET Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations.

, , , , , , , , , , , and . DRC, page 1-2. IEEE, (2018)

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Vandana Muyal

Fu-Chang Chang

Sheng-Chia Chang

William Ockham's view on human capability. Uni Frankfurt Main, (2009)

Liang-Zung Chang

Pao-Yüan Chang

 

Other publications of authors with the same name

OPTIMO: A 65-nm 279-GOPS/W 16-b Programmable Spatial-Array Processor with On-Chip Network for Solving Distributed Optimizations via the Alternating Direction Method of Multipliers., , , and . IEEE J. Solid State Circuits, 55 (3): 629-638 (2020)Efficient Signal Reconstruction via Distributed Least Square Optimization on a Systolic FPGA Architecture., , , , and . ICASSP, page 1493-1497. IEEE, (2019)A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range., , , , , , and . ISSCC, page 1-3. IEEE, (2022)A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 59 (1): 52-64 (January 2024)EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 56 (1): 136-150 (2021)A 2.38 MCells/mm2 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation., , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking., , , , , , , , , and 1 other author(s). ISSCC, page 426-427. IEEE, (2023)A 65nm Image Processing SoC Supporting Multiple DNN Models and Real-Time Computation-Communication Trade-Off Via Actor-Critical Neuro-Controller., , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)A 65nm Thermometer-Encoded Time/Charge-Based Compute-in-Memory Neural Network Accelerator at 0.735pJ/MAC and 0.41pJ/Update., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (4): 1408-1412 (2021)Neuromorphic Swarm on RRAM Compute-in-Memory Processor for Solving QUBO Problem., , , , , and . DAC, page 1-6. IEEE, (2023)