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Power reduction techniques for an 8-core xeon® processor.

, , , , , , , , , и . ESSCIRC, стр. 340-343. IEEE, (2009)

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Keval Vora

Sujal Ghosh

Gerhard Voran

Bernd-Jürgen Vorath

Walter Voraß

 

Другие публикации лиц с тем же именем

A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache., , , , , , , , , и 2 other автор(ы). IEEE J. Solid State Circuits, 42 (1): 17-25 (2007)SkyLake-SP: A 14nm 28-Core xeon® processor., , , , , , , , , и 2 other автор(ы). ISSCC, стр. 34-36. IEEE, (2018)Power reduction techniques for an 8-core xeon® processor., , , , , , , , , и . ESSCIRC, стр. 340-343. IEEE, (2009)A 22 nm 15-Core Enterprise Xeon® Processor Family., , , , , , , , , и . IEEE J. Solid State Circuits, 50 (1): 35-48 (2015)Clock Generation and Distribution of a Dual-Core Xeon Processor with 16MB L3 Cache., , , , , и . ISSCC, стр. 1512-1521. IEEE, (2006)5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family., , , , , , , , , и . ISSCC, стр. 102-103. IEEE, (2014)A 45 nm 8-Core Enterprise Xeon¯ Processor., , , , , , , , , и . IEEE J. Solid State Circuits, 45 (1): 7-14 (2010)Cascade Lake: Next Generation Intel Xeon Scalable Processor., , , , , , , , , и 1 other автор(ы). IEEE Micro, 39 (2): 29-36 (2019)Innovative practices session 10C: Delay test., , , и . VTS, стр. 1. IEEE Computer Society, (2013)