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Disambiguation of "Kameyama, Michitaka"

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Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling.

, , and . IEICE Trans. Electron., 91-C (4): 479-486 (2008)

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Michitaka Ota

Shin'ichi Kameyama

 

Other publications of authors with the same name

An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture., , , and . ASP-DAC, page 89-90. IEEE, (2011)Low-power multiple-valued current-mode integrated circuit with current-source control and its application., , and . ASP-DAC, page 413-418. IEEE, (1997)Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products., and . ICRA, page 3691-3696. IEEE Computer Society, (1998)A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment., and . APCCAS, page 1803-1806. IEEE, (2006)Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit., , , and . ISCAS, page 3017-3020. IEEE, (2012)Performance evaluation of a multivalued rsa encryption vlsi., , and . Syst. Comput. Jpn., 22 (7): 12-21 (1991)Multi-valued current-mode parallel multiplier based on redundant positive-digit number representations., , , , , and . Syst. Comput. Jpn., 24 (5): 40-52 (1993)Design of a Highly Parallel Ultrahigher-Valued Logic Network Based on a Bio-Device Model., , and . Syst. Comput. Jpn., 21 (9): 1-12 (1990)Robot Vision VLSI Processor for the Rectangular Solid Representation of 3-Dimensional Objects., , and . J. Robotics Mechatronics, 8 (6): 501-507 (1996)VLSI Computer for Robotics., and . J. Robotics Mechatronics, 1 (1): 68-73 (1989)