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Experiments with a Program Timing Tool Based on Source-Level Timing Schema.

, and . RTSS, page 72-81. IEEE Computer Society, (1990)

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A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor., , , and . SCOPES, volume 3199 of Lecture Notes in Computer Science, page 244-258. Springer, (2004)An Accurate Worst Case Timing Analysis for RISC Processors., , , , , , , , , and . IEEE Trans. Software Eng., 21 (7): 593-604 (1995)Threaded Prefetching: A New Instruction Memory Hierarchy for Real-Time Systems., , , , and . Real Time Syst., 13 (1): 47-65 (1997)Developing an asynchronous NoAck-based full-duplex MAC for IEEE 802.11 networks in a systems approach.. Comput. Commun., (2021)A Practical Unacknowledged Unicast Transmission in IEEE 802.11 Networks., , , and . KSII Trans. Internet Inf. Syst., 5 (3): 523-541 (2011)Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemtive Scheduling., , , , , , , , and . IEEE Trans. Computers, 47 (6): 700-713 (1998)Mobility-Aware Interference Avoidance Scheme for Vehicular WLANs., , , , , , and . KSII Trans. Internet Inf. Syst., 5 (12): 2272-2293 (2011)Adjusting the Retry Limit for Congestion Control in an Overlapping Private BSS Environment.. KSII Trans. Internet Inf. Syst., 8 (6): 1881-1900 (2014)Analysis of cache-related preemption delay in fixed-priority preemptive scheduling., , , , , , , and . RTSS, page 264-274. IEEE Computer Society, (1996)Worst Case Timing Analysis of RISC Processors: R3000/R3010 Case Study., , , , , , , , and . RTSS, page 308-319. IEEE Computer Society, (1995)