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Design and Realization of a New Signal Security System for Multimedia Data Transmission.

, , , and . EURASIP J. Adv. Signal Process., 2003 (13): 1291-1305 (2003)

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An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model., , , , and . DAC, page 652-657. IEEE, (2007)Dynamic voltage domain assignment technique for low power performance manageable cell based design., , , and . ASP-DAC, page 359-360. IEEE, (2010)Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism., , , , and . ASP-DAC, page 85-86. IEEE, (2011)Recognizing Chinese Texts with 3D Convolutional Neural Network., , , and . ICIP, page 2120-2123. IEEE, (2019)Real-Time 3D Depth Generation for Stereoscopic Video Applications with Thread-Level Superscalar-Pipeline Parallelization., , , and . J. Signal Process. Syst., 72 (1): 17-33 (2013)An efficient design for one-dimensional discrete Hartley transform using parallel additions.. IEEE Trans. Signal Process., 48 (10): 2806-2813 (2000)A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique., , , and . ISCAS, page 3139-3142. IEEE, (2007)A CORDIC-based VLSI Array for Computing 2-D Discrete Hartley Transform., , and . ISCAS, page 1571-1574. IEEE, (1993)A High Throughput Deblocking Filter Design Supporting Multiple Video Coding Standards., , and . ISCAS, page 2377-2380. IEEE, (2009)Design of a new signal security system., and . ISCAS (4), page 121-124. IEEE, (2002)