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RRAM Computing-in-Memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge Inference.

L. Wang, J. An, W. Ye, W. Li, H. Gao, Y. He, J. Gao, J. Yue, L. Fan, and C. Dou. APCCAS, page 497-500. IEEE, (2022)

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Jinshan Liu

Jinshan Zhang

Haidi Yue

Chaofang Yue

Jenny Yuen

Other publications of authors with the same name

PACA: A Pattern Pruning Algorithm and Channel-Fused High PE Utilization Accelerator for CNNs.J. Wang, S. Yu, Z. Yuan, J. Yue, Z. Yuan, R. Liu, Y. Wang, H. Yang, X. Li, and Y. Liu. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 5043-5056 (2022)Accuracy Optimization With the Framework of Non-Volatile Computing-In-Memory Systems.Y. Huang, Y. He, J. Yue, H. Yang, and Y. Liu. IEEE Trans. Circuits Syst. I Regul. Pap., 69 (2): 518-529 (2022)CORAL: Coarse-grained reconfigurable architecture for Convolutional Neural Networks.Z. Yuan, Y. Liu, J. Yue, J. Li, and H. Yang. ISLPED, page 1-6. IEEE, (2017)High Area/Energy Efficiency RRAM CNN Accelerator with Pattern-Pruning-Based Weight Mapping Scheme.S. Yu, L. Zhang, J. Wang, J. Yue, Z. Yuan, X. Li, H. Yang, and Y. Liu. NVMSA, page 1-6. IEEE, (2021)Sparsity-Aware Non-Volatile Computing-In-Memory Macro with Analog Switch Array and Low-Resolution Current-Mode ADC.Y. Huang, Y. He, J. Yue, W. Sun, H. Yang, and Y. Liu. ASP-DAC, page 684-689. IEEE, (2022)RL Based Network Accelerator Compiler for Joint Compression Hyper-Parameter Search.X. Feng, J. Yue, Z. Yuan, H. Yang, and Y. Liu. ISCAS, page 1-5. IEEE, (2020)A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating.J. Yue, X. Feng, Y. He, Y. Huang, Y. Wang, Z. Yuan, M. Zhan, J. Liu, J. Su, Y. Chung and 7 other author(s). ISSCC, page 238-240. IEEE, (2021)Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead.H. Li, Y. Liu, C. Fu, C. Xue, D. Xiang, J. Yue, J. Li, D. Zhang, J. Hu, and H. Yang. DAC, page 156:1-156:6. ACM, (2016)Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers.Z. Yuan, J. Yue, H. Yang, Z. Wang, J. Li, Y. Yang, Q. Guo, X. Li, M. Chang, H. Yang and 1 other author(s). VLSI Circuits, page 33-34. IEEE, (2018)A Sparse-Adaptive CNN Processor with Area/Performance balanced N-Way Set-Associate PE Arrays Assisted by a Collision-Aware Scheduler.Z. Yuan, J. Wang, Y. Yang, J. Yue, Z. Wang, X. Feng, Y. Wang, X. Li, H. Yang, and Y. Liu. A-SSCC, page 61-64. IEEE, (2019)

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Disambiguation of "Yue, Jinshan"

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RRAM Computing-in-Memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge Inference.

Please choose a person to relate this publication to

Jinshan Liu

Jinshan Zhang

Haidi Yue

Chaofang Yue

Jenny Yuen

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yue, Jinshan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML RRAM Computing-in-Memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge Inference.

Please choose a person to relate this publication to

Jinshan Liu

Jinshan Zhang

Haidi Yue

Chaofang Yue

Jenny Yuen

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

RRAM Computing-in-Memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge Inference.