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An Effective At-Speed Scan Testing Approach Using Multiple-Timing Clock Waveforms.

H. Iwata, Y. Maeda, J. Matsushima, and M. Takakura. Asian Test Symposium, page 1. IEEE Computer Society, (2012)

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Jun Jun Lu

Meta Jun

Jun Yamamoto

Jun Yang

Other publications of authors with the same name

A 16 nm FinFET Heterogeneous Nona-Core SoC Supporting ISO26262 ASIL B Standard.S. Shibahara, C. Takahashi, K. Fukuoka, Y. Kitaji, T. Irita, H. Hara, Y. Shimazaki, and J. Matsushima. IEEE J. Solid State Circuits, 52 (1): 77-88 (2017)A New Framework for RTL Test Points Insertion Facilitating a "Shift-Left DFT" Strategy.H. Iwata, Y. Maeda, J. Matsushima, O. Laouamri, N. Khanna, J. Mayer, and N. Mukherjee. ITC, page 1-10. IEEE, (2023)Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST.S. Wang, T. Aono, Y. Higami, H. Takahashi, H. Iwata, Y. Maeda, and J. Matsushima. ATS, page 155-160. IEEE, (2018)A yield improvement methodology based on logic redundant repair with a repairable scan flip-flop designed by push rule.M. Kurimoto, J. Matsushima, S. Ohbayashi, and Y. Fukui. ISQED, page 184-190. IEEE, (2010)Innovative practices on test in Japan.K. Asami, Y. Tamura, H. Kobayashi, J. Matsushima, Y. Maeda, and K. Hatayama. VTS, page 1. IEEE Computer Society, (2018)Automotive Functional Safety Assurance by POST with Sequential Observation.S. Wang, Y. Higami, H. Takahashi, H. Iwata, and J. Matsushima. IEEE Des. Test, 35 (3): 39-45 (2018)Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation.S. Wang, H. Al-Awadhi, S. Hamada, Y. Higami, H. Takahashi, H. Iwata, and J. Matsushima. ATS, page 209-214. IEEE Computer Society, (2016)A Power Reduction Method for Scan Testing in Ultra-Low Power Designs.H. Iwata, Y. Maeda, and J. Matsushima. ATS, page 141. IEEE, (2021)Multi-configuration Scan Structure for Various Purposes.H. Iwata, and J. Matsushima. ATS, page 131. IEEE Computer Society, (2016)CooLBIST: An Effective Approach of Test Power Reduction for LBIST.J. Matsushima, Y. Maeda, and M. Takakura. ATS, page 264. IEEE Computer Society, (2008)

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Disambiguation of "Matsushima, Jun"

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An Effective At-Speed Scan Testing Approach Using Multiple-Timing Clock Waveforms.

Please choose a person to relate this publication to

Jun Jun Lu

Meta Jun

Jun Yamamoto

Jun Yang

Jun Yang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Matsushima, Jun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An Effective At-Speed Scan Testing Approach Using Multiple-Timing Clock Waveforms.

Please choose a person to relate this publication to

Jun Jun Lu

Meta Jun

Jun Yamamoto

Jun Yang

Jun Yang

Other publications of authors with the same name

Disambiguation

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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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An Effective At-Speed Scan Testing Approach Using Multiple-Timing Clock Waveforms.