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A Comprehensive BIST Solution for Polar Transceivers Using On-Chip Resources.

, , , , , and . ACM Trans. Design Autom. Electr. Syst., 23 (1): 2:1-2:21 (2017)

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Soft Error Resilient System Design through Error Correction., , , , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 143-156. Springer, (2006)Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors., , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (12): 2322-2325 (2011)Sequential Element Design With Built-In Soft Error Resilience., , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (12): 1368-1378 (2006)Clock Faults Induced Min and Max Delay Violations., , , , and . J. Electron. Test., 30 (1): 111-123 (2014)Invited Talk 1: Testing of Power Constraint Computing.. ATS, page 6. IEEE, (2007)Cache RAM inductive fault analysis with fab defect modeling., , , , , , and . ITC, page 862-871. IEEE Computer Society, (1998)Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint., , , and . ICCAD, page 191-196. ACM, (2009)An industrial case study for X-canceling MISR., , , and . ITC, page 1-10. IEEE Computer Society, (2009)Can Clock Faults be Detected Through Functional Test?, , , , and . DDECS, page 168-173. IEEE Computer Society, (2006)Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors., , and . DFT, page 63-70. IEEE Computer Society, (2003)