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Self-Checking Voter for High Speed TMR Systems., , and . J. Electron. Test., 21 (4): 377-389 (2005)Novel on-chip circuit for jitter testing in high-speed PLLs., , and . IEEE Trans. Instrum. Meas., 54 (5): 1779-1788 (2005)Accurate Linear Model for SET Critical Charge Estimation., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (8): 1161-1166 (2009)Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation., , , , and . IOLTS, page 17-22. IEEE Computer Society, (2006)Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop., , and . IOLTS, page 17-24. IEEE Computer Society, (2004)The Other Side of the Timing Equation: a Result of Clock Faults., , , , and . DFT, page 169-177. IEEE Computer Society, (2005)Clock Faults Induced Min and Max Delay Violations., , , , and . J. Electron. Test., 30 (1): 111-123 (2014)Fault tolerant techniques for electronic systems implemented by nanometer technology.. University of Bologna, Italy, (2006)Can Clock Faults be Detected Through Functional Test?, , , , and . DDECS, page 168-173. IEEE Computer Society, (2006)Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects., , , and . DATE, page 170-175. European Design and Automation Association, Leuven, Belgium, (2006)