Author of the publication

Intra-Macro Data Reuse.

J. Yue, Z. Yuan, X. Feng, Y. He, Z. Zhang, X. Si, R. Liu, M. Chang, X. Li, H. Yang, and Y. Liu. ISSCC, page 234-236. IEEE, (2020)

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Si Gangyan

Si Yang

Zhongyi Si

Han Si

Yuefang Si

Other publications of authors with the same name

MLFlash-CIM: Embedded Multi-Level NOR-Flash Cell based Computing in Memory Architecture for Edge AI Devices.S. Zeng, Y. Zhang, Z. Zhu, Z. Qin, C. Dou, X. Si, and Q. Li. AICAS, page 1-4. IEEE, (2021)SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation.B. Wang, C. Xue, H. Liu, X. Li, A. Yin, Z. Feng, Y. Kong, T. Xiong, H. Hsu, Y. Zhou and 4 other author(s). ISCAS, page 3383-3387. IEEE, (2022)A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.A. Guo, X. Si, X. Chen, F. Dong, X. Pu, D. Li, Y. Zhou, L. Ren, Y. Xue, X. Dong and 9 other author(s). ISSCC, page 128-129. IEEE, (2023)Design Challenges and Methodology of High-Performance SRAM-Based Compute-in-Memory for AI Edge Devices.Y. Wang, Y. Zhou, B. Wang, T. Xiong, Y. Kong, and X. Si. UCET, page 47-52. IEEE, (2021)A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs.Z. Zhang, Z. Liu, F. Liu, Y. Gao, Y. Ma, Y. Zhang, A. Guo, T. Xiong, J. Chen, X. Chen and 6 other author(s). CICC, page 1-2. IEEE, (2024)Complementary Series-connected STT-MTJ for Time-based Computing-in-Memory.R. Zhou, B. Liu, X. Si, and H. Cai. ISCAS, page 1-5. IEEE, (2024)14.2 Proactive Voltage Droop Mitigation Using Dual-Proportional-Derivative Control Based on Current and Voltage Prediction Applied to a Multicore Processor in 28nm CMOS.W. Shan, K. Zhou, K. Li, Y. Du, Z. Chen, J. Qian, H. Ge, J. Yang, and X. Si. ISSCC, page 256-258. IEEE, (2024)A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors.Z. Zhang, J. Chen, X. Si, Y. Tu, J. Su, W. Huang, J. Wang, W. Wei, Y. Chiu, J. Hong and 6 other author(s). A-SSCC, page 217-218. IEEE, (2019)15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.X. Si, Y. Tu, W. Huang, J. Su, P. Lu, J. Wang, T. Liu, S. Wu, R. Liu, Y. Chou and 17 other author(s). ISSCC, page 246-248. IEEE, (2020)16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips.J. Su, Y. Chou, R. Liu, T. Liu, P. Lu, P. Wu, Y. Chung, L. Hung, J. Ren, T. Pan and 11 other author(s). ISSCC, page 250-252. IEEE, (2021)

BibSonomy

Disambiguation of "Si, Xin"