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Disambiguation of "Chattopadhyay, Anupam"

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Spintronic Device-Structure for Low-Energy XOR Logic using Domain Wall Motion.

, and . ISCAS, page 1-5. IEEE, (2019)

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Anupam Chattopadhyay

Anupam Singh

Anupam Karmakar

Anupam Sengupta

Dhrupadi Chattopadhyay

 

Other publications of authors with the same name

Towards Designing a Secure RISC-V System-on-Chip: ITUS., , , , , , and . J. Hardw. Syst. Secur., 4 (4): 329-342 (2020)Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization., , , , , and . IEEE Trans. Parallel Distributed Syst., 29 (8): 1707-1720 (2018)Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design., , , , , and . CoRR, (2016)Machine Learning based Blind Side-Channel Attacks on PQC-based KEMs - A Case Study of Kyber KEM., , , and . IACR Cryptol. ePrint Arch., (2024)Efficient Hardware Accelerator for AEGIS-128 Authenticated Encryption., and . Inscrypt, volume 8957 of Lecture Notes in Computer Science, page 385-402. Springer, (2014)A RISC-V SoC with Hardware Trojans: Case Study on Trojan-ing the On-Chip Protocol Conversion., , and . VLSI-SoC, page 1-6. IEEE, (2023)Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks., , , , and . DATE, page 561-564. IEEE, (2021)Hardware Security Primitives Using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs., , , , , and . ASP-DAC, page 449-454. ACM, (2023)Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGA., , , , and . VLSID, page 257-262. IEEE, (2019)Crack me if you can: hardware acceleration bridging the gap between practical and theoretical cryptanalysis?: a Survey., , , and . SAMOS, page 167-172. ACM, (2018)