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RaPiD: AI Accelerator for Ultra-low Precision Training and Inference.

S. Venkataramani, V. Srinivasan, W. Wang, S. Sen, J. Zhang, A. Agrawal, M. Kar, S. Jain, A. Mannari, H. Tran, Y. Li, E. Ogawa, K. Ishizaki, H. Inoue, M. Schaal, M. Serrano, J. Choi, X. Sun, N. Wang, C. Chen, A. Allain, J. Bonanno, N. Cao, R. Casatuta, M. Cohen, B. Fleischer, M. Guillorn, H. Haynie, J. Jung, M. Kang, K. Kim, S. Koswatta, S. Lee, M. Lutz, S. Mueller, J. Oh, A. Ranjan, Z. Ren, S. Rider, K. Schelm, M. Scheuermann, J. Silberman, J. Yang, V. Zalani, X. Zhang, C. Zhou, M. Ziegler, V. Shah, M. Ohara, P. Lu, B. Curran, S. Shukla, L. Chang, and K. Gopalakrishnan. ISCA, page 153-166. IEEE, (2021)

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Vijayalakshmi Sethuraman

R Srinivasan

Sadagopan Srinivasan

Srinivasan Rajaraman

Srinivasan Seetharaman

Other publications of authors with the same name

RECAP: A region-based cure for the common cold (cache).J. Zebchuk, H. Cain, X. Tong, V. Srinivasan, and A. Moshovos. HPCA, page 83-94. IEEE Computer Society, (2013)Evaluating the performance of active cache management schemes.E. Tam, J. Rivers, V. Srinivasan, G. Tyson, and E. Davidson. ICCD, page 368-375. IEEE Computer Society, (1998)Co-designing accelerators and SoC interfaces using gem5-Aladdin.Y. Shao, S. Xi, V. Srinivasan, G. Wei, and D. Brooks. MICRO, page 48:1-48:12. IEEE Computer Society, (2016)Workload-aware Automatic Parallelization for Multi-GPU DNN Training.S. Shin, Y. Jo, J. Choi, S. Venkataramani, V. Srinivasan, and W. Sung. CoRR, (2018)SAFER: Stuck-At-Fault Error Recovery for Memories.N. Seong, D. Woo, V. Srinivasan, J. Rivers, and H. Lee. MICRO, page 115-124. IEEE Computer Society, (2010)ScaleCom: Scalable Sparsified Gradient Compression for Communication-Efficient Distributed Training.C. Chen, J. Ni, S. Lu, X. Cui, P. Chen, X. Sun, N. Wang, S. Venkataramani, V. Srinivasan, W. Zhang and 1 other author(s). NeurIPS, (2020)Hardware solutions to reduce effective memory access time.V. Srinivasan. University of Michigan, USA, (2001)Scalable high performance main memory system using phase-change memory technology.M. Qureshi, V. Srinivasan, and J. Rivers. ISCA, page 24-33. ACM, (2009)RaPiD: AI Accelerator for Ultra-low Precision Training and Inference.S. Venkataramani, V. Srinivasan, W. Wang, S. Sen, J. Zhang, A. Agrawal, M. Kar, S. Jain, A. Mannari, H. Tran and 44 other author(s). ISCA, page 153-166. IEEE, (2021)A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.J. Oh, S. Lee, M. Kang, M. Ziegler, J. Silberman, A. Agrawal, S. Venkataramani, B. Fleischer, M. Guillorn, J. Choi and 33 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)

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Disambiguation of "Srinivasan, Vijayalakshmi"

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RaPiD: AI Accelerator for Ultra-low Precision Training and Inference.

Please choose a person to relate this publication to

Vijayalakshmi Sethuraman

R Srinivasan

Sadagopan Srinivasan

Srinivasan Rajaraman

Srinivasan Seetharaman

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Srinivasan, Vijayalakshmi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML RaPiD: AI Accelerator for Ultra-low Precision Training and Inference.

Please choose a person to relate this publication to

Vijayalakshmi Sethuraman

R Srinivasan

Sadagopan Srinivasan

Srinivasan Rajaraman

Srinivasan Seetharaman

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
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RaPiD: AI Accelerator for Ultra-low Precision Training and Inference.