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Investigation on NBTI-induced dynamic variability in nanoscale CMOS devices: Modeling, experimental evidence, and impact on circuits.

, , , , , , , and . Microelectron. Reliab., (2018)

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OMI/TMI-based Modeling and Fast Simulation of Random Telegraph Noise (RTN) in Advanced Logic Devices and Circuits., , , , , , and . ASICON, page 1-4. IEEE, (2019)Evaluation of SRAM Vmin shift induced by random telegraph noise (RTN): physical understanding and prediction method., , , , , and . ISCAS, page 1-4. IEEE, (2018)Layout-dependent aging mitigation for critical path timing., , , , , , , and . ASP-DAC, page 153-158. IEEE, (2018)Towards reliability-aware circuit design in nanoscale FinFET technology: - New-generation aging model and circuit reliability simulator., , , , , , , , , and 2 other author(s). ICCAD, page 780-785. IEEE, (2017)Investigation on NBTI-induced dynamic variability in nanoscale CMOS devices: Modeling, experimental evidence, and impact on circuits., , , , , , , and . Microelectron. Reliab., (2018)How close to the CMOS voltage scaling limit for FinFET technology? - Near-threshold computing and stochastic computing., , , and . ASICON, page 56-59. IEEE, (2017)Circuit Reliability Comparison Between Stochastic Computing and Binary Computing., , , , , and . IEEE Trans. Circuits Syst., 67-II (12): 3342-3346 (2020)Investigation on the amplitude coupling effect of random telegraph noise (RTN) in nanoscale FinFETs., , , , , , and . IRPS, page 6-1. IEEE, (2018)