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Disambiguation of "Yang, Lita"

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Bit Error Tolerance of a CIFAR-10 Binarized Convolutional Neural Network Processor.

, , , , and . ISCAS, page 1-5. IEEE, (2018)

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Lita Lilikwargawidjaja

Rita Anita Litauszky

Beáta Litauszki

Lita Plagemann

Lita Vespermann

 

Other publications of authors with the same name

BinarEye: An always-on energy-accuracy-scalable binary CNN processor with all memory on chip in 28nm CMOS., , , , and . CICC, page 1-4. IEEE, (2018)SRAM voltage scaling for energy-efficient convolutional neural networks., and . ISQED, page 7-12. IEEE, (2017)11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint., , , , , , , , , and 3 other author(s). ISSCC, page 210-212. IEEE, (2024)Pushing the Limits of Narrow Precision Inferencing at Cloud Scale with Microsoft Floating Point., , , , , , , , , and 14 other author(s). NeurIPS, (2020)Bit Error Tolerance of a CIFAR-10 Binarized Convolutional Neural Network Processor., , , , and . ISCAS, page 1-5. IEEE, (2018)Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications., , , , , , , , and . IEEE Micro, 42 (6): 116-124 (2022)TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs., , , , , , , , , and 2 other author(s). DAC, page 74:1-74:10. ACM, (2018)Mixed-signal circuits for embedded machine-learning applications., , , , and . ACSSC, page 1341-1345. IEEE, (2015)An Always-On 3.8 $\mu$ J/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS., , , , and . IEEE J. Solid State Circuits, 54 (1): 158-172 (2019)Approximate SRAM for Energy-Efficient, Privacy-Preserving Convolutional Neural Networks., and . ISVLSI, page 689-694. IEEE Computer Society, (2017)