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Author Rebuttal to Rocha et al. "Comments on Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks".

, and . J. Signal Process. Syst., 81 (1): 135-136 (2015)

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RLWS: A Reinforcement Learning based GPU Warp Scheduler., , , , and . CoRR, (2017)Advances in Software Pipelining., and . The Compiler Design Handbook, 2nd ed., CRC Press, (2007)Unified Instruction Reordering and Algebraic Transformations for Minimum Cost Offset Assignment., and . SCOPES, volume 2826 of Lecture Notes in Computer Science, page 270-284. Springer, (2003)Design and Performance Evaluation of EXMAN: An EXtended MANchester Data Flow Computer., , and . IEEE Trans. Computers, 35 (3): 229-244 (1986)Taming warp divergence., and . CGO, page 50-60. ACM, (2017)Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding, , and . J. VLSI Signal Process. Syst., 44 (3): 245--267 (2006)Author Rebuttal to Rocha et al. "Comments on Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks"., and . J. Signal Process. Syst., 81 (1): 135-136 (2015)Data Flow Implementation of Generalized Guarded Commands., and . PARLE (1), volume 505 of Lecture Notes in Computer Science, page 372-389. Springer, (1991)A Theory for Co-Scheduling Hardware and Software Pipelines in ASIPs and Embedded Processors., , and . Des. Autom. Embed. Syst., 6 (3): 243-275 (2002)MicroRefresh: Minimizing Refresh Overhead in DRAM Caches., , and . MEMSYS, page 350-361. ACM, (2016)