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Disambiguation of "Nomura, Masahiro"

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Variation-aware subthreshold logic circuit design.

, , , , , and . ASICON, page 1-4. IEEE, (2013)

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Toru Nomura

Masahiro Noguchi

Masahiro Ogawa

Yutaka Nomura

Masahiro Yoshida

 

Other publications of authors with the same name

A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates., , , , , , and . DAC, page 984-989. ACM, (2011)Warm Starting CMA-ES for Hyperparameter Optimization., , , , and . AAAI, page 9188-9196. AAAI Press, (2021)Efficient Hyperparameter Optimization under Multi-Source Covariate Shift., and . CIKM, page 1376-1385. ACM, (2021)Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits., , , , , and . CICC, page 1-4. IEEE, (2012)Natural Evolution Strategy for Unconstrained and Implicitly Constrained Problems with Ridge Structure., and . SSCI, page 1-7. IEEE, (2021)CatCMA : Stochastic Optimization for Mixed-Category Problems., , , , and . GECCO, ACM, (2024)13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO., , , , , , , and . ISSCC, page 486-488. IEEE, (2012)12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics., , , , , , and . ISLPED, page 163-168. IEEE/ACM, (2011)Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS., , , , , , and . ISLPED, page 21-26. IEEE/ACM, (2011)24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits., , , , , , , , , and 2 other author(s). ISQED, page 586-591. IEEE, (2012)