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Scan-Out Power Reduction for Logic BIST.

, , , и . IEICE Trans. Inf. Syst., 96-D (9): 2012-2020 (2013)

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Kohei Tatsumi

Kohei Tatsumi

Mohamed Koheil

Susanne Koheil

 

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A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits., , , , , , , и . VTS, стр. 197-202. IEEE Computer Society, (2012)On Improving Defect Coverage of Stuck-at Fault Tests., , , , и . Asian Test Symposium, стр. 216-223. IEEE Computer Society, (2005)A Method of Static Test Compaction Based on Don't Care Identification., , и . DELTA, стр. 392-395. IEEE Computer Society, (2002)On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression., , , , , и . VLSI Design, стр. 279-284. IEEE Computer Society, (2013)Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory., , и . IOLTS, стр. 226-227. IEEE, (2018)Scan-Out Power Reduction for Logic BIST., , , и . IEICE Trans. Inf. Syst., 96-D (9): 2012-2020 (2013)A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing., , , , и . IEICE Trans. Inf. Syst., 94-D (4): 833-840 (2011)High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme., , , , , , , и . IEICE Trans. Inf. Syst., 93-D (1): 2-9 (2010)CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing., , , , , , , и . Asian Test Symposium, стр. 99-104. IEEE Computer Society, (2009)Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling., , , , , , , , , и 1 other автор(ы). Asian Test Symposium, стр. 90-95. IEEE Computer Society, (2011)