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Disambiguation of "Rayas-Sánchez, José Ernesto"

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Analysis of the implications of stacked devices in nano-scale technologies for analog applications.

, , and . LATS, page 1-4. IEEE, (2017)

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Juan José Sánchez

José Sánchez Murillo

José Sánchez Meseguer

José Uriarte Sánchez

José Alvarez Sánchez

 

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Systematic configuration of coarsely discretized 3D EM solvers for reliable and fast simulation of high-frequency planar structures., , , and . LASCAS, page 1-4. IEEE, (2013)Design of experiments implementation towards optimization of power distribution networks., , and . LASCAS, page 1-4. IEEE, (2017)Direct optimization of a PCI express link equalization in industrial post-silicon validation., , , and . LATS, page 1-6. IEEE, (2018)Impedance matching analysis and EMC validation of a low-cost PCB differential interconnect., , and . LATS, page 1-5. IEEE Computer Society, (2015)A digital predistortion technique based on a NARX network to linearize GaN class F power amplifiers., , , , , , and . MWSCAS, page 717-720. IEEE, (2014)Frequency- and Time-Domain Yield Optimization of a Power Delivery Network Subject to Large Decoupling Capacitor Tolerances., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (12): 5610-5620 (2022)Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (4): 733-740 (2019)Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation., , and . ITC, page 1-10. IEEE, (2018)Machine Learning Techniques and Space Mapping Approaches to Enhance Signal and Power Integrity in High-Speed Links and Power Delivery Networks., , , , and . LASCAS, page 1-4. IEEE, (2020)Analysis of the implications of stacked devices in nano-scale technologies for analog applications., , and . LATS, page 1-4. IEEE, (2017)