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Disambiguation of "Gaillardon, Pierre-Emmanuel"

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Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology.

, , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 339-351 (2016)

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Pierre-Emmanuel Arduin

Pierre-Emmanuel Leni

Pierre Emmanuel Ilouga

Pierre-Emmanuel Cornilleau

Emmanuel Lule

 

Other publications of authors with the same name

Post-P&R Performance and Power Analysis for RRAM-Based FPGAs., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 639-650 (2018)Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only)., , , , and . FPGA, page 262. ACM, (2015)Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors., and . VLSI-SoC, page 107-112. IEEE, (2018)A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors., , , and . VLSI-SoC (Selected Papers), volume 586 of IFIP Advances in Information and Communication Technology, page 307-322. Springer, (2019)End-to-end Automatic Logic Optimization Exploration via Domain-specific Multi-armed Bandit., , , and . CoRR, (2022)A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal., , , , and . CoRR, (2021)GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment., , , , , , and . MICRO, page 334-346. ACM, (2019)Smart-Redundancy With In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (8): 1204-1213 (August 2023)Extending Boolean Methods for Scalable Logic Synthesis., , , , , , and . IEEE Access, (2020)Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (5): 2028-2036 (May 2023)