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Disambiguation of "Yu, Zhiyi"

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The write deduplication mechanism based on a novel low-power data latched sense amplifier for a magnetic tunnel junction based non-volatile memory.

, , and . ASICON, page 383-386. IEEE, (2017)

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Zhiyi Ding

Zhiyi Lv

Yu-Ting Yu

Yu-Yu Su

Sze-Man Yu

Metal complexes with enolatoimine ligands for controlled olefin polymerizations. Uni Konstanz, (2009)
 

Other publications of authors with the same name

A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer., , , , , and . CICC, page 1-4. IEEE, (2015)A 2D mesh NoC with self-configurable and shared-FIFOs routers., , , , and . ASICON, page 1-4. IEEE, (2013)A fast multi-core virtual platform and its application on software development., , , , and . ASICON, page 1-4. IEEE, (2013)A Shared Memory Module for Asynchronous Arrays of Processors., , and . EURASIP J. Embed. Syst., (2007)Architecture and Evaluation of an Asynchronous Array of Simple Processors., , , , , , , , and . J. Signal Process. Syst., 53 (3): 243-259 (2008)Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (5): 963-970 (2013)Hand gesture recognition algorithm combining hand-type adaptive algorithm and effective-area ratio for efficient edge computing., , , , and . J. Electronic Imaging, (2021)A Low Insertion Loss Wideband Bonding-Wire Based Interconnection for 400 Gbps PAM4 Transceivers., , and . IEICE Trans. Electron., 106 (1): 14-19 (2023)DM-IMCA: A dual-mode in-memory computing architecture for general purpose processing., , , , , , , and . IEICE Electron. Express, 17 (4): 20200005 (2020)NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators., , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (9): 1966-1978 (2020)