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LMStr: exploring shared hardware controlled scratchpad memory for multicores.

, , , and . MEMSYS, page 152-165. ACM, (2017)

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An Idealistic Neuro-PPM Branch Predictor., , , , and . J. Instruction-Level Parallelism, (2007)Exploring Chapel Productivity Using Some Graph Algorithms., , , , , and . IPDPS Workshops, page 672. IEEE, (2020)MetaStrider: Architectures for Scalable Memory-centric Reduction of Sparse Data Streams., , , , , and . ACM Trans. Archit. Code Optim., 16 (4): 35:1-35:26 (2020)SortCache: Intelligent Cache Management for Accelerating Sparse Data Workloads., , , , and . ACM Trans. Archit. Code Optim., 18 (4): 56:1-56:24 (2021)A Performance Analysis of Phantom-Cell Adaptive Mesh Refinement on CPUs and GPUs., , , and . J. Comput. Inf. Sci. Eng., (2021)A statistical performance model of the opteron processor., , and . SIGMETRICS Perform. Evaluation Rev., 38 (4): 75-80 (2011)StAdHyTM: A Statically Adaptive Hybrid Transactional Memory: A scalability study on large parallel graphs., , and . CCWC, page 1-7. IEEE, (2017)Compiler-Directed Functional Unit Shutdown for Microarchitecture Power Optimization., , and . IPCCC, page 372-379. IEEE Computer Society, (2007)Superstrider associative array architecture: Approved for unlimited unclassified release: SAND2017-7089 C., , , and . HPEC, page 1-7. IEEE, (2017)DyAdHyTM: A Low Overhead Dynamically Adaptive Hybrid Transactional Memory on Big Data Graphs., , and . CoRR, (2017)