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Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks., , , and . ETS, page 1-6. IEEE, (2019)Fast static compaction of tests composed of independent sequences: basic properties and comparison of methods., , and . ICECS, page 445-448. IEEE, (2002)Automatic SoC Level Test Path Synthesis Based on Partial Functional Models., , , and . Asian Test Symposium, page 532-538. IEEE Computer Society, (2011)On-line fault classification and handling in IEEE1687 based fault management system for complex SoCs., , and . LATS, page 69-74. IEEE, (2016)Invited paper: System-wide fault management based on IEEE P1687 IJTAG., , and . ReCoSoC, page 1-4. IEEE, (2011)Learning Digital Test and Diagnostics via Internet., , , , , and . Int. J. Online Eng., (2007)On-Chip Sensors Data Collection and Analysis for SoC Health Management., , , , and . DFT, page 1-6. IEEE, (2023)SoC and Board Modeling for Processor-Centric Board Testing., , , and . DSD, page 575-582. IEEE Computer Society, (2011)Fault Simulation with Parallel Critical Path Tracing for Combinatorial Circuits Using Structurally Synthesized BDDs., , , and . LATW, page 97-102. IEEE, (2006)Structural fault collapsing by superposition of BDDs for test generation in digital circuits., , , and . ISQED, page 250-257. IEEE, (2010)