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Automating Test-Suite Augmentation., , , and . QSIC, page 67-72. IEEE, (2014)The 3rd Reactive Synthesis Competition (SYNTCOMP 2016): Benchmarks, Participants & Results., , , , , , , , , and 6 other author(s). SYNT@CAV, volume 229 of EPTCS, page 149-177. (2016)Debugging formal specifications using simple counterstrategies., , and . FMCAD, page 152-159. IEEE, (2009)Synthesizing cooperative reactive mission plans., , and . IROS, page 3478-3485. IEEE, (2015)Synthesizing adaptive test strategies from temporal logic specifications., , , , , , and . Formal Methods Syst. Des., 55 (2): 103-135 (2019)Debugging formal specifications: a practical approach using model-based diagnosis and counterstrategies., , and . Int. J. Softw. Tools Technol. Transf., 15 (5-6): 563-583 (2013)A Fast and Cache-Timing Resistant Implementation of the AES.. CT-RSA, volume 4964 of Lecture Notes in Computer Science, page 187-202. Springer, (2008)Synthesizing Robust Systems with RATSY, , , , and . SYNT, volume 84 of EPTCS, page 47-53. (2012)Synthesizing adaptive test strategies from temporal logic specifications., , , and . FMCAD, page 17-24. IEEE, (2016)Synthesis of Admissible Shields., , , and . CoRR, (2019)