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Disambiguation of "Chuang, Ching-Te"

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Impacts of NBTI and PBTI on Power-gated SRAM with High-k Metal-gate Devices.

, , and . ISCAS, page 377-380. IEEE, (2009)

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Shih-Te Chuang

Ching-yao Chuang

Ching-Ho Chuang

Wilhelm Ching

Paisal Chingduang

 

Other publications of authors with the same name

Modeling and Analysis of Leakage Currents in Double-Gate Technologies., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (10): 2052-2061 (2006)A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control., , , , , , , , , and 9 other author(s). SoCC, page 197-200. IEEE, (2011)Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application., , , , and . SoCC, page 18-23. IEEE, (2016)Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells., , , and . ISCAS, page 1122-1125. IEEE, (2014)Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells., , and . ISLPED, page 242-247. ACM, (2016)A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies., , , , and . ISLPED, page 8-13. ACM, (2007)Low temperature (<180 °C) bonding for 3D integration., , , , , , , , , and 1 other author(s). 3DIC, page 1-5. IEEE, (2013)Stability and performance optimization of InGaAs-OI and GeOI hetero-channel SRAM cells., , , and . ESSDERC, page 77-80. IEEE, (2012)A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line., , , , , , and . Microelectron. J., (2016)Reducing parasitic BJT effects in partially depleted SOI digital logic circuits., , and . Microelectron. J., 39 (2): 275-285 (2008)