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A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET.

M. Raj, Y. Frans, S. Ambatipudi, D. Mahashin, P. Heyn, S. Balakrishnan, J. Campenhout, J. Grayson, M. Epitaux, and K. Chang. VLSI Circuits, page 190-. IEEE, (2019)

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Jürgen Davids

Volker David

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A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET.J. Im, K. Zheng, C. Chou, L. Zhou, J. Kim, S. Chen, Y. Wang, H. Hung, K. Tan, W. Lin and 11 other author(s). IEEE J. Solid State Circuits, 56 (1): 7-18 (2021)50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET.M. Raj, Y. Frans, P. Chiang, S. Ambatipudi, D. Mahashin, P. Heyn, S. Balakrishnan, J. Campenhout, J. Grayson, M. Epitaux and 1 other author(s). ECOC, page 1-4. IEEE, (2020)Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET.M. Raj, Y. Frans, P. Chiang, S. Ambatipudi, D. Mahashin, P. Heyn, S. Balakrishnan, J. Campenhout, J. Grayson, M. Epitaux and 1 other author(s). IEEE J. Solid State Circuits, 55 (4): 1086-1095 (2020)A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET.J. Im, S. Chen, D. Freitas, A. Chou, L. Zhou, I. Zhuang, T. Cronin, D. Mahashin, W. Lin, K. Chan and 7 other author(s). VLSI Circuits, page 145-146. IEEE, (2018)6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET.J. Im, K. Zheng, A. Chou, L. Zhou, J. Kim, S. Chen, Y. Wang, H. Hung, K. Tan, W. Lin and 11 other author(s). ISSCC, page 116-118. IEEE, (2020)A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET.M. Raj, Y. Frans, S. Ambatipudi, D. Mahashin, P. Heyn, S. Balakrishnan, J. Campenhout, J. Grayson, M. Epitaux, and K. Chang. VLSI Circuits, page 190-. IEEE, (2019)A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET.J. Hudner, D. Carey, R. Casey, K. Hearne, P. de Abreu Farias Neto, I. Chlis, M. Erett, C. Poon, A. Laraba, H. Zhang and 5 other author(s). VLSI Circuits, page 47-48. IEEE, (2018)A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies.M. Raj, C. Xie, A. Bekele, A. Chou, W. Zhang, Y. Cao, J. Kim, N. Narang, H. Zhao, Y. Wang and 7 other author(s). ISSCC, page 204-205. IEEE, (2023)

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Disambiguation of "Mahashin, David"

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A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET.

Please choose a person to relate this publication to

Jürgen Davids

Volker David

Bodo David

Erich David

Ernst David

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Mahashin, David"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET.

Please choose a person to relate this publication to

Jürgen Davids

Volker David

Bodo David

Erich David

Ernst David

Other publications of authors with the same name

Disambiguation

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URL
DOI
BibTeX
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APA
Chicago
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A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET.