Author of the publication

Memory Efficient JPEG 2000 Architecture With Stripe Pipeline Scheduling.

, , , and . IEEE Trans. Signal Process., 54 (12): 4807-4816 (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor., , , , and . DAC, page 90-95. ACM, (2008)Memory Efficient JPEG 2000 Architecture With Stripe Pipeline Scheduling., , , and . IEEE Trans. Signal Process., 54 (12): 4807-4816 (2006)124 MSamples/s Pixel-Pipelined Motion-JPEG 2000 Codec Without Tile Memory., , , , and . IEEE Trans. Circuits Syst. Video Techn., 17 (4): 398-406 (2007)Precompression Quality-Control Algorithm for JPEG 2000., , , , and . IEEE Trans. Image Processing, 15 (11): 3279-3293 (2006)iVisual: An Intelligent Visual Sensor SoC With 2790 fps CMOS Image Sensor and 205 GOPS/W Vision Processor., , , and . IEEE J. Solid State Circuits, 44 (1): 127-135 (2009)On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform., , , , and . IEEE Trans. Circuits Syst. Video Techn., 17 (7): 814-822 (2007)Design and Implementation of JPEG 2000 Codec with Bit-Plane Scalable Architecture., , , , and . SiPS, page 428-433. IEEE, (2006)Multimode Embedded Compression Codec Engine for Power-Aware Video Coding System., , and . IEEE Trans. Circuits Syst. Video Techn., 19 (2): 141-150 (2009)Application Layer Error Correction Scheme for Video Header Protection on Wireless Network., , , , , and . ISM, page 499-505. IEEE Computer Society, (2005)Scalable Rate-Distortion-Computation Hardware Accelerator for MCTF and ME., , , and . ICME, page 365-368. IEEE Computer Society, (2006)