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A 28Gb/s transceiver with chirp-managed EDC for DML systems., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 264-266. IEEE, (2018)A 0.2-1.45-GHz Subsampling Fractional-N Digital MDLL With Zero-Offset Aperture PD-Based Spur Cancellation and In Situ Static Phase Offset Detection., , и . IEEE J. Solid State Circuits, 52 (3): 799-811 (2017)Area-Efficient QC-LDPC Decoder Architecture Based on Stride Scheduling and Memory Bank Division., и . IEICE Trans. Commun., 96-B (7): 1772-1779 (2013)CIM-Spin: A Scalable CMOS Annealing Processor With Digital In-Memory Spin Operators and Register Spins for Combinatorial Optimization Problems., , и . IEEE J. Solid State Circuits, 57 (7): 2263-2273 (2022)A Reconfigurable lsing Machine for Boolean Satisfiability Problems Featuring Many-Body Spin Interactions., , и . CICC, стр. 1-2. IEEE, (2023)A 32x32 Time-Domain Wavefront Computing Accelerator for Path Planning and Scientific Simulations., , , , и . CICC, стр. 1-2. IEEE, (2021)Two-step beat frequency quantizer based ADC with adaptive reference control for low swing bio-potential signals., , и . CICC, стр. 1-4. IEEE, (2015)A fully-digital beat-frequency based ADC achieving 39dB SNDR for a 1.6mVpp input signal., , и . CICC, стр. 1-4. IEEE, (2013)Mixed-Signal Circuits and Architectures for Energy-Efficient In-Memory and In-Sensor Computation of Artificial Neural Networks.. SoCC, стр. 475-478. IEEE, (2019)A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter., , и . IEEE J. Solid State Circuits, 49 (4): 1017-1026 (2014)