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Reliability Analysis of a Delay-Locked Loop Under HCI and BTI Degradation., и . IRPS, стр. 1-6. IEEE, (2019)GNN-Based Hierarchical Annotation for Analog Circuits., , , , , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (9): 2801-2814 (сентября 2023)Machine Learning Techniques in Analog Layout Automation., , , , , , , , , и 3 other автор(ы). ISPD, стр. 71-72. ACM, (2021)Aging of Current DACs and its Impact in Equalizer Circuits., , , и . IRPS, стр. 1-6. IEEE, (2021)Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models., , , , , , , , , и . ASP-DAC, стр. 158-163. ACM, (2021)ALIGN: A System for Automating Analog Layout., , , , , , , , , и 4 other автор(ы). CoRR, (2020)ALIGN: A System for Automating Analog Layout., , , , , , , , , и 4 other автор(ы). IEEE Des. Test, 38 (2): 8-18 (2021)GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits., , , , , , , , , и . DATE, стр. 55-60. IEEE, (2020)A solitary protection measure against scan chain, fault injection, and power analysis attacks on AES., , и . MWSCAS, стр. 575-578. IEEE, (2017)The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk)., , , , , , , , , и 3 other автор(ы). ICCAD, стр. 54:1-54:2. IEEE, (2020)