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Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization.

F. Niu, Q. Zhou, H. Yao, Y. Cai, J. Yang, and C. Sze. ACM Great Lakes Symposium on VLSI, page 199-204. ACM, (2011)

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Jian Cai

Xuediao Cai

Cuifang Cai

Lu Cai

Dengke Cai

Other publications of authors with the same name

Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain.Y. Cai, J. Shi, Z. Luo, and X. Hong. J. Comput. Sci. Technol., 20 (2): 224-230 (2005)A novel fine-grain track routing approach for routability and crosstalk optimization.Z. Qi, Q. Zhou, Y. Jia, Y. Cai, Z. Li, and H. Yao. ISQED, page 621-626. IEEE, (2011)Design-Rule-Aware Congestion Model with Explicit Modeling of Vias and Local Pin Access Paths.Z. Qi, Y. Cai, and Q. Zhou. J. Comput. Sci. Technol., 30 (3): 614-628 (2015)Priority-Based Routing Resource Assignment Considering Crosstalk.Y. Cai, B. Liu, Y. Xiong, Q. Zhou, and X. Hong. J. Comput. Sci. Technol., 21 (6): 913-921 (2006)A new splitting graph construction algorithm for SIAR router.J. Zhao, H. Yao, Y. Cai, and Q. Zhou. ASICON, page 1-4. IEEE, (2013)Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs.B. Liu, Y. Cai, Q. Zhou, and X. Hong. ASP-DAC, page 582-587. IEEE, (2006)Efficient model reduction of interconnects via double gramians approximation.B. Yan, S. Tan, G. Chen, and Y. Cai. ASP-DAC, page 25-30. IEEE, (2010)A thermal-driven force-directed floorplanning algorithm for 3D ICs.Y. Huang, Q. Zhou, Y. Cai, and H. Yan. CAD/Graphics, page 497-502. IEEE, (2009)SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips.Q. Wang, W. He, H. Yao, T. Ho, and Y. Cai. ISPD, page 49-56. ACM, (2015)Temperature-Aware Electromigration Analysis with Current-Tracking in Power Grid Networks.J. Wang, Y. Cai, and Q. Zhou. J. Comput. Sci. Technol., 36 (5): 1133-1144 (2021)

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Disambiguation of "Cai, Yici"

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Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization.

Please choose a person to relate this publication to

Jian Cai

Xuediao Cai

Cuifang Cai

Lu Cai

Dengke Cai

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Cai, Yici"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization.

Please choose a person to relate this publication to

Jian Cai

Xuediao Cai

Cuifang Cai

Lu Cai

Dengke Cai

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization.