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Flow Cache Cleansing with FPGA Hash Pipe for Highly Stabilized Software Data Plane., , , , , , , , , and . HPSR, page 1-6. IEEE, (2018)Fingerprint Verification Using Perturbation Method., , , and . MVA, page 424-427. (2007)10G/1G dual-rate EPON OLT LSI with dual encryption modes alternated using DBA-information-based algorithm control., , , , , and . ISOCC, page 357-360. IEEE, (2011)Hash-table and balanced-tree based FIB architecture for CCN routers., , , , , , and . ISOCC, page 67-68. IEEE, (2016)Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI., , , , , , , and . IEICE Trans. Electron., 90-C (10): 1892-1899 (2007)Fingerprint Image Enhancement by Pixel-Parallel Processing., , , , , , , and . ICPR (3), page 752-755. IEEE Computer Society, (2002)Lagopus FPGA - A reprogrammable data plane for high-performance software SDN switches., , , and . Hot Chips Symposium, page 1. IEEE, (2015)Fingerprint Image Enhancement and Rotation Schemes for a Single-Chip Fingerprint Sensor and Identifier., , , , , , , , , and . IEICE Trans. Electron., 89-C (4): 540-550 (2006)A Fingerprint Verification Algorithm Using the Differential Matching Rate., , , , , , and . ICPR (3), page 799-802. IEEE Computer Society, (2002)A 500-dpi cellular-logic processing array for fingerprint-image enhancement and verification., , , , , , , , and . CICC, page 261-264. IEEE, (2002)