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Disambiguation of "Nitta, Koyo"

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Flow Cache Cleansing with FPGA Hash Pipe for Highly Stabilized Software Data Plane.

, , , , , , , , , and . HPSR, page 1-6. IEEE, (2018)

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Ryukyo Nitta

Suteera Nittayananta

 

Other publications of authors with the same name

A 4: 2: 2P@ML MPEG-2 video encoder board using an enhanced MP@ML video encoder LSI., , , , and . IEEE Trans. Consumer Electronics, 45 (4): 1130-1133 (1999)Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture., , , , , , , and . COOL CHIPS, page 1-3. IEEE, (2019)Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture., , and . IEICE Trans. Commun., 103-B (1): 11-19 (2020)A Power Reduction Scheme with Partial Sleep Control of ONU Frame Buffer in Operation., , and . IEICE Trans. Commun., 104-B (5): 481-489 (2021)OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization., , , , , , , and . MWSCAS, page 1-4. IEEE, (2022)An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture., , , , , , , and . COOL CHIPS, page 1-3. IEEE, (2022)Video Service Function Chaining with a Real-time Packet Reordering Circuit., , and . ISCAS, page 1-5. IEEE, (2018)Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level., , , , , , , , , and 3 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 15 (9): 1055-1059 (2007)An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding Architecture., , , , , , , and . IEICE Trans. Electron., 106 (6): 312-320 (June 2023)Programmable Hardware Accelerator for Finite-State-Machine Processing in Flexible Access Network Systems., , , and . IEICE Trans. Commun., 104-B (3): 277-285 (2021)