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Design of MOS transconductors with low noise and low harmonic distortion for minimum current consumption.

, , , , and . Integr., 40 (3): 365-379 (2007)

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A Novel Concept for a Hybrid 140 Mbit/s System., , and . IEEE Trans. Commun., 27 (10): 1584-1593 (1979)Design of MOS transconductors with low noise and low harmonic distortion for minimum current consumption., , , , and . Integr., 40 (3): 365-379 (2007)A CMOS V-I converter with 75-dB SFDR and 360-μW power consumption., , , , and . IEEE J. Solid State Circuits, 40 (7): 1527-1532 (2005)Analysis and design of high-performance asynchronous sigma-delta Modulators with a binary quantizer., , , , and . IEEE J. Solid State Circuits, 41 (3): 588-596 (2006)Analysis of Phase-Locked Timing Extraction Circuits for Pulse Code Transmission.. IEEE Trans. Commun., 22 (9): 1236-1249 (1974)A Practical Design Approach to Decision Feedback Receivers with Conventional Filters.. IEEE Trans. Commun., 26 (5): 679-689 (1978)An Experimental 560 Mbits/s Repeater with Integrated Circuits., and . IEEE Trans. Commun., 25 (9): 995-1004 (1977)CMOS V-I converter with 75dB SFDR and 360μW power consumption., , , , and . ESSCIRC, page 235-238. IEEE, (2004)Design of high-performance asynchronous sigma delta modulators with a binary quantizer with hysteresis., , , , and . CICC, page 181-184. IEEE, (2004)Video-rate D/A converter using reduced rate sigma-delta modulation., and . CICC, page 241-244. IEEE, (1998)