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Improving System Predictability and Performance via Hardware Accelerated Data Structures., , , , , , and . ICCS, volume 9 of Procedia Computer Science, page 1197-1205. Elsevier, (2012)Exploring Area/Delay Tradeoffs in an AES FPGA Implementation., , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 575-585. Springer, (2004)Enhancing Compiler Techniques for Memory Energy Optimizations., , and . EMSOFT, volume 2491 of Lecture Notes in Computer Science, page 364-381. Springer, (2002)k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator., , , , , and . EIT, page 257-263. IEEE, (2015)An FPGA-based Hardware Accelerator for Iris Segmentation., , and . ReConFig, page 1-8. IEEE, (2018)Design and Implementation of an FPGA Architecture for High-Speed Network Feature Extraction., , , , and . FPT, page 49-56. IEEE, (2007)An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (1): 113-123 (2012)A Reconfigurable Architecture for the Detection of Strongly Connected Components., , , and . ACM Trans. Reconfigurable Technol. Syst., 9 (2): 16:1-16:19 (2016)Securing Multimedia Content Using Joint Compression and Encryption., , and . IEEE Multim., 20 (4): 50-61 (2013)Scalable FastMDP for Pre-departure Airspace Reservation and Strategic De-conflict., , and . CoRR, (2020)