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Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications., , , , , , и . ISSCC, стр. 94-95. IEEE, (2009)An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 18 (7): 1043-1056 (2010)Asynchronous Parallel Prefix Computation., и . IEEE Trans. Computers, 47 (11): 1244-1252 (1998)Asynchronous Circuits and Systems in Superconducting RSFQ Digital Technology., , , и . ASYNC, стр. 274-. IEEE Computer Society, (1998)Active Guardband Management in Power7+ to Save Energy and Maintain Reliability., , , , , , , и . IEEE Micro, 33 (4): 35-45 (2013)A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS., , , , , и . IEEE J. Solid State Circuits, 47 (12): 3220-3231 (2012)A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation., , , , , , , , , и . FPGA, стр. 153-162. ACM, (2012)Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion., , , , , , , , , и 4 other автор(ы). CICC, стр. 1-4. IEEE, (2013)A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI., , , , , , , и . ISSCC, стр. 400-401. IEEE, (2013)A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS., , , , , и . ISSCC, стр. 516-517. IEEE, (2008)