From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM., , , , и . ISLPED, стр. 1-6. IEEE, (2019)Phase Noise Impairment and Environment-Adaptable Fast (EAF) Optimization for Programming of Reconfigurable Radio Frequency (RF) Receivers., , , , , , и . GLOBECOM, стр. 1-6. IEEE, (2015)Minimizing Area and Energy of Deep Learning Hardware Design Using Collective Low Precision and Structured Compression., , , , , и . CoRR, (2018)Vesti: An In-Memory Computing Processor for Deep Neural Networks Acceleration., , , , , и . ACSSC, стр. 1516-1521. IEEE, (2019)Compact Modeling of IGZO-based CAA-FETs with Time-zero-instability and BTI Impact on Device and Capacitor-less DRAM Retention Reliability., , , , , , , , , и 7 other автор(ы). VLSI Technology and Circuits, стр. 300-301. IEEE, (2022)Improving DNN Hardware Accuracy by In-Memory Computing Noise Injection., , , , , , и . IEEE Des. Test, 39 (4): 71-80 (2022)PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference., , , , , , , , , и . VLSI Circuits, стр. 1-2. IEEE, (2021)Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data., , , , , , и . ASP-DAC, стр. 441-446. IEEE, (2015)XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks., , , и . IEEE J. Solid State Circuits, 55 (6): 1733-1743 (2020)Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 28 (1): 48-61 (2020)