( en | de | ru )

 

Disambiguation of "Seok, Mingoo"

Author of the publication

copydeleteadd this publication to your clipboard
Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks.

, , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (1): 48-61 (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

In-Deok Seok

Joon-Weon Seok

Dong-Seok Tschoe

Ghil-Seok Yang

Han Seok Seo

 

Other publications of authors with the same name

8.2 Fully integrated low-drop-out regulator based on event-driven PI control., and . ISSCC, page 148-149. IEEE, (2016)A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines., , , , and . A-SSCC, page 129-132. IEEE, (2016)Exploring Variability and Performance in a Sub-200-mV Processor., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 43 (4): 881-891 (2008)Ultra-Compact and Robust Physically Unclonable Function Based on Voltage-Compensated Proportional-to-Absolute-Temperature Voltage Generators., and . IEEE J. Solid State Circuits, 51 (9): 2192-2202 (2016)A Millimeter-Scale Energy-Autonomous Sensor System With Stacked Battery and Solar Cells., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (3): 801-813 (2013)C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism., , , and . IEEE J. Solid State Circuits, 55 (7): 1888-1897 (2020)MemNet: Memory-Efficiency Guided Neural Architecture Search with Augment-Trim learning., , , , and . CoRR, (2019)0.5-1-V, 90-400-mA, Modular, Distributed, 3 × 3 Digital LDOs Based on Event-Driven Control and Domino Sampling and Regulation., , , , , and . IEEE J. Solid State Circuits, 56 (9): 2781-2794 (2021)DIMCA: An Area-Efficient Digital In-Memory Computing Macro Featuring Approximate Arithmetic Hardware in 28 nm., , , , , , and . IEEE J. Solid State Circuits, 59 (3): 960-971 (March 2024)A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip., , , , , , and . IEEE J. Solid State Circuits, 59 (2): 616-625 (February 2024)