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Minimizing Area and Energy of Deep Learning Hardware Design Using Collective Low Precision and Structured Compression.

S. Yin, G. Srivastava, S. Venkataramanaiah, C. Chakrabarti, V. Berisha, and J. sun Seo. CoRR, (2018)

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Aman K K Bhasin

K Böhm

K Schaber

K Beheng

K Schweizerhof

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Minimizing Area and Energy of Deep Learning Hardware Design Using Collective Low Precision and Structured Compression.S. Yin, G. Srivastava, S. Venkataramanaiah, C. Chakrabarti, V. Berisha, and J. sun Seo. CoRR, (2018)FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro.J. Saikia, A. Sridharan, I. Yeo, S. Venkataramanaiah, D. Fan, and J. Seo. ESSCIRC, page 405-408. IEEE, (2023)Deep Neural Network Training Accelerator Designs in ASIC and FPGA.S. Venkataramanaiah, S. Yin, Y. Cao, and J. Seo. ISOCC, page 21-22. IEEE, (2020)FixyNN: Energy-Efficient Real-Time Mobile Computer Vision Hardware Acceleration via Transfer Learning.P. Whatmough, C. Zhou, P. Hansen, S. Venkataramanaiah, J. sun Seo, and M. Mattina. MLSys, mlsys.org, (2019)Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection on Resource-Constrained FPGA.H. Suh, J. Meng, T. Nguyen, S. Venkataramanaiah, V. Kumar, Y. Cao, and J. sun Seo. FPT, page 1-9. IEEE, (2021)FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory.S. Venkataramanaiah, H. Suh, S. Yin, E. Nurvitadhi, A. Dasu, Y. Cao, and J. Seo. ICCAD, page 74:1-74:8. IEEE, (2020)FixyNN: Efficient Hardware for Mobile Computer Vision via Transfer Learning.P. Whatmough, C. Zhou, P. Hansen, S. Venkataramanaiah, J. sun Seo, and M. Mattina. CoRR, (2019)Minimizing area and energy of deep learning hardware design using collective low precision and structured compression.S. Yin, G. Srivastava, S. Venkataramanaiah, C. Chakrabarti, V. Berisha, and J. sun Seo. ACSSC, page 1907-1911. IEEE, (2017)Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations.S. Yin, S. Venkataramanaiah, G. Chen, R. Krishnamurthy, Y. Cao, C. Chakrabarti, and J. sun Seo. BioCAS, page 1-5. IEEE, (2017)

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Disambiguation of "Venkataramanaiah, Shreyas K."

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Minimizing Area and Energy of Deep Learning Hardware Design Using Collective Low Precision and Structured Compression.

Please choose a person to relate this publication to

Aman K K Bhasin

K Böhm

K Schaber

K Beheng

K Schweizerhof

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Venkataramanaiah, Shreyas K."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Minimizing Area and Energy of Deep Learning Hardware Design Using Collective Low Precision and Structured Compression.

Please choose a person to relate this publication to

Aman K K Bhasin

K Böhm

K Schaber

K Beheng

K Schweizerhof

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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Chicago
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Minimizing Area and Energy of Deep Learning Hardware Design Using Collective Low Precision and Structured Compression.