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A 270ps 20mW 108-bit End-around Carry Adder for Multiply-Add Fused Floating Point Unit.

, , , , , and . J. Signal Process. Syst., 58 (2): 139-144 (2010)

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A low latency and low power dynamic Carry Save Adder., , , , , , , and . ISCAS (2), page 477-480. IEEE, (2004)Leading-Zero Anticipator (LZA) in the IBM RISC System/6000 Floating-Point Execution Unit., and . IBM J. Res. Dev., 34 (1): 71-77 (1990)A decompression core for PowerPC., , , , and . IBM J. Res. Dev., 42 (6): 807-812 (1998)Performance and power evaluation of an in-line accelerator., , , , , and . Conf. Computing Frontiers, page 81-82. ACM, (2010)A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2011)IBM second-generation RISC machine organization., , , , , , , , , and 3 other author(s). ICCD, page 138-142. IEEE, (1989)Processor architecture for software implementation of multi-sector G-RAKE receivers for HSUPA wireless infrastructure., , , , , and . ICASSP, page 2770-2774. IEEE, (2013)Design of the IBM RISC System/6000 Floating-Point Execution Unit., , and . IBM J. Res. Dev., 34 (1): 59-70 (1990)Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processor., , , , , , and . HPCA, page 423-432. IEEE Computer Society, (2012)A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI., , , , , , , and . ISSCC, page 400-401. IEEE, (2013)