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Disambiguation of "Kim, Tony Tae-Hyoung"

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A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications.

, , , and . IEEE Open J. Circuits Syst., (2021)

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Hyoung-Gook Kim

Moo-Hyoung Kim

Hyoung Seok Kim

Hyoung-Soo Kim

Tae-hy Kim

 

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A 0.4-V, 0.138-fJ/Cycle Single-Phase-Clocking Redundant-Transition-Free 24T Flip-Flop With Change-Sensing Scheme in 40-nm CMOS., , , and . IEEE J. Solid State Circuits, 53 (10): 2806-2817 (2018)A multi-story power delivery technique for 3D integrated circuits., , , and . ISLPED, page 57-62. ACM, (2008)Leakage Control System Using Data Estimation of Resistive Memory., , , and . ISOCC, page 196-197. IEEE, (2018)A 213.7-µW Gesture Sensing System-On-Chip With Self-Adaptive Motion Detection and Noise-Tolerant Outermost-Edge-Based Feature Extraction in 65 nm., , , , and . ESSCIRC, page 123-126. IEEE, (2019)An 8T SRAM with BTI-Aware Stability Monitor and two-phase write operation for cell stability improvement in 28-nm FDSOI., , , and . ESSCIRC, page 437-440. IEEE, (2016)A Scalable Bit-Serial Computing Hardware Accelerator for Solving 2D/3D Partial Differential Equations Using Finite Difference Method., , , and . ESSCIRC, page 353-356. IEEE, (2022)A Graph-Based Accelerator of Retinex Model with Bit-Serial Computing for Image Processing., , , , , and . ISCAS, page 1-5. IEEE, (2023)Design and array implementation a cantilever-based non-volatile memory utilizing vibrational reset., , , , , and . ESSDERC, page 284-287. IEEE, (2013)An Ultra-low Power 8T SRAM with Vertical Read Word Line and Data Aware Write Assist., , , and . A-SSCC, page 1-2. IEEE, (2018)A Configurable Randomness Enhanced RRAM PUF with Biased Current Sensing Scheme., , and . ISCAS, page 1-5. IEEE, (2021)