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Genome Sequence Alignment - Design Space Exploration for Optimal Performance and Energy Architectures.

, , , , , , and . IEEE Trans. Computers, 70 (12): 2218-2233 (2021)

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Gem5-X: A Gem5-Based System Level Simulation Framework to Optimize Many-Core Platforms., , , , and . SpringSim, page 1-12. IEEE, (2019)Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures., , , , , and . LASCAS, page 1-4. IEEE, (2022)ALPINE: Analog In-Memory Acceleration With Tight Processor Integration for Deep Learning., , , , , , , , and . IEEE Trans. Computers, 72 (7): 1985-1998 (July 2023)BLADE: An in-Cache Computing Architecture for Edge Devices., , , , , and . IEEE Trans. Computers, 69 (9): 1349-1363 (2020)Accelerating Inference on Binary Neural Networks with Digital RRAM Processing., , , , , , , and . VLSI-SoC (Selected Papers), volume 586 of IFIP Advances in Information and Communication Technology, page 257-278. Springer, (2019)ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning., , , , , , , , and . CoRR, (2022)Energy proportionality in near-threshold computing servers and cloud data centers: Consolidating or Not?, , , , , , and . DATE, page 147-152. IEEE, (2018)Genome Sequence Alignment - Design Space Exploration for Optimal Performance and Energy Architectures., , , , , , and . IEEE Trans. Computers, 70 (12): 2218-2233 (2021)Gem5-X: A Many-core Heterogeneous Simulation Platform for Architectural Exploration and Optimization., , , , and . ACM Trans. Archit. Code Optim., 18 (4): 44:1-44:27 (2021)A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories., , , , , , , and . VLSI-SoC, page 160-165. IEEE, (2019)