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s Write Throughput at Tj of 170°C.

Y. Taito, T. Kono, M. Nakano, T. Saito, T. Ito, K. Noguchi, H. Hidaka, and T. Yamauchi. IEEE J. Solid State Circuits, 51 (1): 213-221 (2016)

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Hideto Hiramatsu

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A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs.T. Ooishi, M. Asakura, S. Tomishima, H. Hidaka, K. Arimoto, and K. Fujishima. IEEE J. Solid State Circuits, 29 (4): 432-440 (April 1994)The cache DRAM architecture: a DRAM with an on-chip cache memory.H. Hidaka, Y. Matsuda, M. Asakura, and K. Fujishima. IEEE Micro, 10 (2): 14-25 (1990)A built-in self-repair analyzer (CRESTA) for embedded DRAMs.T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka. ITC, page 567-574. IEEE Computer Society, (2000)How future mobility meets IT: Cyber-physical system designs revisit semiconductor technology.H. Hidaka. A-SSCC, page 1-4. IEEE, (2015)A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C.Y. Taito, T. Kono, M. Nakano, T. Saito, T. Ito, K. Noguchi, H. Hidaka, and T. Yamauchi. IEEE J. Solid State Circuits, 51 (1): 213-221 (2016)Non-Volatile Memories.H. Hidaka, and Y. Sofer. ISSCC, page 470-471. IEEE, (2007)A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications.S. Tomishima, T. Tsuji, T. Kawasaki, M. Ishikawa, T. Inokuchi, H. Kato, H. Tanizaki, W. Abe, A. Shibayama, Y. Fukushima and 9 other author(s). IEEE J. Solid State Circuits, 36 (11): 1728-1737 (2001)A shared built-in self-repair analysis for multiple embedded memories.J. Ohtani, T. Ooishi, T. Kawagoe, M. Niiro, M. Maruta, and H. Hidaka. CICC, page 187-190. IEEE, (2001)Session 1 overview: Plenary session.A. Chandrakasan, and H. Hidaka. ISSCC, page 7-9. IEEE, (2012)Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode.Y. Nishimura, M. Hamada, H. Hidaka, H. Ozaki, K. Fujishima, and Y. Hayasaka. ITC, page 826-829. IEEE Computer Society, (1986)

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Hideto Hiramatsu

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