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Register file exploration for a multi-standard wireless forward error correction ASIP., and . SiPS, page 024-029. IEEE, (2009)Software-Controlled Scratchpad Mapping Strategies for Wavelet-Based Applications., , , , , , , and . SiPS, page 362-367. IEEE, (2006)Nonlinear transformations for high level regular array ASIC synthesis., , and . VLSI Signal Processing, 4 (4): 259-268 (1992)Accuracy of Quasi-Monte Carlo technique in failure probability estimations., , , , and . ICICDT, page 1-4. IEEE, (2016)Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures., , , , and . IEEE Trans. Computers, 58 (3): 311-321 (2009)Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations., , , , and . ICICDT, page 1-4. IEEE, (2014)Global Multimedia System Design Exploration Using Accurate Memory Organization Feedback., , , , and . DAC, page 327-332. ACM Press, (1999)Systematic intermediate sequence removal for reduced memory accesses., , , and . SCOPES, volume 235 of ACM International Conference Proceeding Series, page 51-60. (2007)Solving large scale assignment problems in high-level synthesis by approximative quadratic programming., , , and . ACM Great Lakes Symposium on VLSI, page 19-24. ACM, (2001)L0 Cluster Synthesis and Operation Shuffling., , , , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 311-321. Springer, (2004)