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Disambiguation of "Mack, Joshua"

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Profile-Guided Parallel Task Extraction and Execution for Domain Specific Heterogeneous SoC.

, , , , , , and . ISPA/BDCloud/SocialCom/SustainCom, page 913-920. IEEE, (2022)

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Joshua Migdal

Joshua Sempebwa

Joshua Cordes

Joshua Amavi

Joshua Müller

 

Other publications of authors with the same name

Accelerated Shadow Detection and Removal Method., , , , , and . AICCSA, page 1-8. IEEE Computer Society, (2019)GPU-RANC: A CUDA Accelerated Simulation Framework for Neuromorphic Architectures., , , , , , and . NICE, page 1-7. IEEE, (2024)A Runtime Manager Integrated Emulation Environment for Heterogeneous SoC Design with RISC-V Cores., , , , , , , and . IPDPS (Workshops), page 23-30. IEEE, (2024)An Ecosystem for Evaluating Domain-Specific System on Chip (DSSoC) Devices: Productive Application Deployment and Scheduling Perspectives.. University of Arizona, Tucson, USA, (2024)base-search.net (ftunivarizona:oai:repository.arizona.edu:10150/672454).DS3: A System-Level Domain-Specific System-on-Chip Simulation Framework., , , , , , , , and . CoRR, (2020)Floating point CORDIC-based architecture for powering computation., , and . ReConFig, page 1-6. IEEE, (2015)CEDR: A Compiler-integrated, Extensible DSSoC Runtime., , , , and . ACM Trans. Embed. Comput. Syst., 22 (2): 36:1-36:34 (March 2023)A Hardware-based HEFT Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCs., , , and . VLSI-SoC, page 1-6. IEEE, (2022)Profile-Guided Parallel Task Extraction and Execution for Domain Specific Heterogeneous SoC., , , , , , and . ISPA/BDCloud/SocialCom/SustainCom, page 913-920. IEEE, (2022)FPGA Based Emulation Environment for Neuromorphic Architectures., , , , , , , , , and . IPDPS Workshops, page 90-97. IEEE, (2020)