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System-level test bench generation in a co-design framework., , , , and . ETW, page 25-30. IEEE Computer Society, (2000)Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug., , , and . IET Comput. Digit. Tech., 4 (2): 104-113 (2010)An experimental analysis of the effectiveness of the circular self-test path technique., , and . EURO-DAC, page 246-251. IEEE Computer Society, (1994)RISC-V-Based Platforms for HPC: Analyzing Non-functional Properties for Future HPC and Big-Data Clusters., , , , , , , , , and 8 other author(s). SAMOS, volume 14385 of Lecture Notes in Computer Science, page 395-410. Springer, (2023)A Reliability-aware Environment for Design Exploration for GPU Devices., , , and . DDECS, page 169-174. IEEE, (2023)A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs., , , , and . ED&TC, page 560-565. IEEE Computer Society, (1997)Exploring the Mysteries of System-Level Test., , , , , , , , , and . ATS, page 1-6. IEEE, (2020)Effective SAT-based Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity in a Pipelined Processor., , , , , and . ATS, page 73-78. IEEE, (2021)Exploiting the Selfish Gene algorithm for evolving hardware cellular automata., , and . CEC, page 1401-1406. IEEE, (2000)Automating the Generation of Functional Stress Inducing Stimuli for Burn-In Testing., , , , , and . ETS, page 1-5. IEEE, (2023)