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A 69.8 dB SNDR 3rd-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver., , , , , , и . CICC, стр. 1-4. IEEE, (2010)A time-domain architecture and design method of high speed A-to-D converters with standard cells., , , , и . A-SSCC, стр. 353-356. IEEE, (2011)Design methods for pipeline & delta-sigma A-to-D converters with convex optimization., , , , , , , , , и . ASP-DAC, стр. 690-695. IEEE, (2009)A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-μm CMOS process., , и . IEEE J. Solid State Circuits, 37 (5): 559-565 (2002)A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells., , , , и . IEICE Trans. Electron., 96-C (6): 813-819 (2013)An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration., , , , , , и . IEEE J. Solid State Circuits, 46 (4): 986-991 (2011)An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects., , , и . IEEE J. Solid State Circuits, 47 (11): 2773-2782 (2012)A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise., , , , , , , и . ISSCC, стр. 272-273. IEEE, (2013)A Low Distortion 3rd-Order Continuous-Time Delta-Sigma Modulator for a Worldwide Digital TV-Receiver., , , , , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (2): 471-478 (2012)A -90 dBc@ 10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit., , , , и . IEICE Trans. Electron., 89-C (6): 739-745 (2006)