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Disambiguation of "Yeric, Greg"

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System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs.

, , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (4): 888-898 (2019)

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Greg Breinholt

Greg Little

Greg Ross

Greg Kiss

Greg Foderaro

 

Other publications of authors with the same name

Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below., , , , , and . IEEE Des. Test Comput., 22 (3): 232-239 (2005)System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (4): 888-898 (2019)DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node., , , , and . ICCD, page 403-410. IEEE Computer Society, (2017)Match-making for monolithic 3D IC: finding the right technology node., , , , and . DAC, page 77:1-77:6. ACM, (2016)Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study., , , , and . ISLPED, page 70-75. ACM, (2016)Self-aligned double patterning aware pin access and standard cell layout co-optimization., , , , and . ISPD, page 101-108. ACM, (2014)The past present and future of design-technology co-optimization., , , , , and . CICC, page 1-8. IEEE, (2013)Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper)., , , , , and . ICCAD, page 999-1004. IEEE, (2017)Standard Cell Library Design and Optimization Methodology for ASAP7 PDK., , , , , and . CoRR, (2018)Extreme Temperature (> 200 °C), Radiation Hard (> 1 Mrad), Dense (sub-50 nm CD), Fast (2 ns write pulses), Non-Volatile Memory Technology., , , , , and . IMW, page 1-4. IEEE, (2022)