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System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs.

, , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (4): 888-898 (2019)

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Full-chip monolithic 3D IC design and power performance analysis with ASAP7 library: (Invited Paper)., , , and . ICCAD, page 1005-1010. IEEE, (2017)Monolithic 3D IC design: Power, performance, and area impact at 7nm., , , , , , , and . ISQED, page 41-48. IEEE, (2016)RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs., , , , , , , , , and 1 other author(s). DAC, page 101. ACM, (2019)Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs., , and . ISPD, page 90-97. ACM, (2018)Full-Chip Electro-Thermal Coupling Extraction and Analysis for Face-to-Face Bonded 3D ICs., , , , , and . ISPD, page 39-46. ACM, (2020)Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs., , , , and . ISPD, page 47-54. ACM, (2020)Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (3): 410-423 (2022)Design automation and testing of monolithic 3D ICs: Opportunities, challenges, and solutions: (Invited paper)., , , and . ICCAD, page 805-810. IEEE, (2017)Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools., , , , , , and . ICCAD, page 130. ACM, (2016)Pin-3D: A Physical Synthesis and Post-Layout Optimization Flow for Heterogeneous Monolithic 3D ICs., , , , and . ICCAD, page 4:1-4:9. IEEE, (2020)