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System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs.

K. Chang, S. Das, S. Sinha, B. Cline, G. Yeric, and S. Lim. IEEE Trans. Very Large Scale Integr. Syst., 27 (4): 888-898 (2019)

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Romy Das

Bio-economic modeling of soil resource conservation in Mid Hill Region of NepalR. Das. Uni Gießen, (2009)

Anita Das

Arabindo Das

Amitabh Das

Kamalendu Das

Other publications of authors with the same name

A Time-Domain Current-Mode MAC Engine for Analogue Neural Networks in Flexible Electronics.M. Douthwaite, F. García-Redondo, P. Georgiou, and S. Das. BioCAS, page 1-4. IEEE, (2019)A high-speed design methodology for inductive coupling links in 3D-ICs.B. Fletcher, S. Das, and T. Mak. DATE, page 497-502. IEEE, (2018)Modeling and characterization of the system-level Power Delivery Network for a dual-core ARM Cortex-A57 cluster in 28nm CMOS.S. Das, P. Whatmough, and D. Bull. ISLPED, page 146-151. IEEE, (2015)A robust FIR filter with in situ error detection.P. Whatmough, I. Darwazeh, D. Bull, S. Das, and D. Kershaw. ISCAS, page 4185-4188. IEEE, (2010)A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS.P. Whatmough, S. Das, and D. Bull. IEEE J. Solid State Circuits, 49 (1): 84-94 (2014)Guest Editorial Special Issue on the 47th European Solid-State Circuits Conference (ESSCIRC).A. Bevilacqua, S. Das, and P. Harpe. IEEE J. Solid State Circuits, 53 (7): 1876-1877 (2018)Significance-Driven Logic Compression for Energy-Efficient Multiplier Design.I. Qiqieh, R. Shafik, G. Tarawneh, D. Sokolov, S. Das, and A. Yakovlev. IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 417-430 (2018)DVFS in loop accelerators using BLADES.G. Dasika, S. Das, K. Fan, S. Mahlke, and D. Bull. DAC, page 894-897. ACM, (2008)A self-tuning DVS processor using delay-error detection and correction.S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, K. Flautner, and T. Mudge. IEEE J. Solid State Circuits, 41 (4): 792-804 (2006)System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs.K. Chang, S. Das, S. Sinha, B. Cline, G. Yeric, and S. Lim. IEEE Trans. Very Large Scale Integr. Syst., 27 (4): 888-898 (2019)

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Disambiguation of "Das, Shidhartha"

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System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs.

Please choose a person to relate this publication to

Romy Das

Anita Das

Arabindo Das

Amitabh Das

Kamalendu Das

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Das, Shidhartha"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs.

Please choose a person to relate this publication to

Romy Das

Anita Das

Arabindo Das

Amitabh Das

Kamalendu Das

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs.